Programmable logic devices, such as field programmable gate arrays, typically include repetitive blocks of logic that interface with each other through a hierarchical interconnect architecture. The blocks of logic generally include one or more look-up tables (LUTs) that are organized into physically and functionally identical units, with each unit referred to as a slice or a logic slice.
Each slice often can implement different functional modes, such as for example a logic mode, an arithmetic ripple mode, a random access memory (RAM) mode, and/or a read only memory (ROM) mode. The memory cells utilized for the RAM mode and the ROM mode are typically the same memory cells that are utilized to implement the LUT in the logic mode or the arithmetic ripple mode.
For example, FIG. 1 shows a block diagram 100 illustrating two conventional slices 102, which for example may be configured as RAM (i.e., traditional slice RAM). Each slice 102 (i.e., slice 102(1) or 102(2)) includes a write port control circuit 104, two LUTs 106 (labeled LUT0 and LUT1 or LUT2 and LUT3), and two registers 108 (labeled Register0 and Register1 or Register 2 and Register3). Slice 102(1) receives a clock (CLK0) signal 110 and slice 102(2) receives a clock (CLK1) signal 112.
A drawback of a typical slice is that a write to the memory cells may be synchronous, but a read from the memory cells is limited to be either asynchronous or synchronous to the same clock as the write clock. For example, each slice typically has only one clock and one clock enable, which makes a dual port RAM mode cumbersome with the read on the two ports either asynchronous or synchronous to the same clock as the write clock. As a result, there is a need for improved memory techniques.